WP 2

WP2 – Process Characterization and PDK Verification, Assessment and Improvement

In this WP, dedicated modelling cells will be designed, laid out, fabricated and tested to assess and/or create the device models required to secure the MMICs design. This will cover both passive devices and transistors for small-signal, large-signal and noise characterization. In addition, device channel temperature will be measured under operating conditions to assist in the proper definition of the reliability test plan (WP4).

UTV, OMMIC and VTT will together define the most convenient test structures, using both the released 100 nm gate length GaN/Si process (D01GH), and the new 60 nm gate length GaN/Si process (D006GH).

OMMIC will fabricate wafers carrying both the D01GH and the D006GH test structures.

UTV and OMMIC will perform on-wafer measurement of the test structures. The characterisation will be carried out up to V-Band (i.e. up to 50 GHz) for large-signal and noise operation and up to 110 GHz for small-signal S-parameters. Such a broad characterization range is selected to ensure the accuracy, usability and effectiveness of the models well within the millimetre-wave frequency range.

UTV, OMMIC and VTT will then compare the measurements with the existing design kit simulated data, and, wherever required, tune the existing models or will extract new models.

OMMIC will then integrate the new and/or modified models in the design kits to make them available for the design of the MMICs proposed within the project.

Samples of the realized active device cells will be tested for the determination of the device junction temperature making use of Raman spectroscopy techniques. The setup for this kind of measurements will be made available by OMMIC partners (Bristol University).