At the beginning of the WP, the functionalities to be investigated and realised will be first identified and the relevant requirements and specifications will be defined. The circuits include both the space qualification related circuits and demonstrators of the technology potentials. The technology to be used for the designs will be predominantly the 100 nm GaN/Si realized by OMMIC (D01GH), that will be qualified for space applications. To this goal, two subsequent foundry runs will be realised, the second one mainly for risk mitigation purposed and fine tuning of the resulting circuit performance. For circuit design, the updated PDK resulting from Task 2.0 will be used, together with the measured data gathered therein.
To further strengthen the potential applications of GaN/Si at millimetre-wave frequencies, a second technology will be also evaluated and adopted for circuit design, featured by 60 nm gate length (D006GH). Given the uniformity and full ownership of each single technological steps by OMMIC, the latter technology can be used in conjunction and simultaneously with the 100 nm one, thus resulting in a mixed 60 nm/100 nm technology, that can be adopted at single circuit/function level. The exceptional flexibility allowed by such unique mixed technology will be exploited in a separated foundry run that will be designed, realized and tested in parallel with the second iteration of 100 nm foundry run.
At the end of the WP, diced demonstrator chips (HPA, LNA, SPDT and SCFE) will be available on one hand to be assembled in the system demonstrator scheduled in WP5.
Furthermore, chips of TCV, DEC and RIC will be available for space evaluation in WP4. In this case both foundry iteration outputs will be used, the first one for preliminary tests, the second one for the proper Space evaluation.