The objective of this task is to define and complete the space evaluation of the OMMIC’s 100 nm GaN/Si (D01GH) semiconductor process. This will be done by subjecting a set of test vehicles (fabricated in the said process) to a series of DC/RF and stress/endurance tests. For the process to be qualified, the test vehicles must pass the various tests according to pass/fail criteria defined in advance of the start of testing.
To achieve the objective:
- the DC/RF and endurance tests per each test vehicle type will be agreed and a test plan containing the pass/failure criteria will be written.
- The test vehicles will be physically and electrically defined, and their assembly to suitable platforms (when necessary) to be compatible with the interfaces of the test systems will be defined. The assemblies will have to be compatible with the environmental conditions of the planned tests.
- The test vehicles will be fabricated in the 100 nm GaN/Si process (Task 3), the platforms manufactured and the test vehicles assembled into the platforms.
- The reliability test campaign has to be carried out with the pass criteria fulfilled.
In this WP therefore the OMMIC 100 nm GaN/Si (D01GH) semiconductor process will be space evaluated. The evaluation is based on a set of tests and analysis, where a set of test vehicles (TCVs, DECs and RICs) are subjected to DC/RF and various endurance tests. The tests, that are applicable to the process in question, will be described in and compiled into a test plan (in conformance to the Basic Specification). Besides the actual qualification tests, the test vehicle assemblies are defined in this Task. The assemblies have to be capable of interfacing with the various test systems needed in the Task. The test vehicles are designed and fabricated in Task 3. The test vehicle assemblies are manufactured and the test vehicles integrated into them in this Task.
VTT will be in overall responsibility of carrying out this work package. The qualification testing is divided between OMMIC (TCVs and DECs) and VTT (RICs). Similarly, OMMIC will be responsible for the TCV and DEC definition and assembly, and VTT for the RIC definition and assembly. OMMIC will be responsible for the reliability test plan definition with VTT providing the RIC testing specific portions. UTV and TAS-I will provide support and useful information to the test plan and RIC assembly definition.
When relevant, the channel temperature will be monitored using the electrical method; this method is based on the measurement of the electrical resistance of the gate; this resistance varying with temperature.